Microelectronic devices used in fabricating integrated circuits are manufactured by employing photolithographic techniques. Fabricating various structures, particularly electronic device structures, typically involves depositing at least one layer of a photosensitive material, generally known as a photoresist material on a substrate. The photoresist material may then be patterned by exposing it to radiation of a certain wavelength to alter characteristics of the photoresist material. In many instances, the radiation is from ultraviolet range of wavelengths causing desired photochemical reactions to occur within the photoresist. The photochemical reactions typically change the solubility characteristics of the photoresist, thereby permitting removal of certain selected portions of the photoresist while maintaining the other portions of the substrate. The selective removal of certain parts of the photoresist allows for protection of certain areas of the substrate while exposing other areas. The portions of the photoresist that remain on the substrate are used as a mask or stencil for processing the underlying substrate.
As methods for producing miniature electronic structures improve, the desire to produce even smaller structures has continued to increase. For instance, the reduction of the FET dimensions has been the primary vehicle pursued to meet the insatiable consumer need for faster electronics. A first-order correlation to faster FET is smaller gate width dimension, and therefore it is called the Critical Dimension (CD). FIG. 1 shows a simple cross-sectional schematic of a FET. There is a thin dielectric 5 between a substrate 1 and a gate electrode 4. A source 2 and drain 3 are doped regions to the sides of the gate. The width of the gate is the CD 6. It is generally known to those skilled in the art that as the CD gets smaller, the FET gets faster.
The dimension of most key features in microelectronics is limited by the dimension of the resist that is printed in a photolithography step. Therefore, the primary focus for producing smaller CDs has been upon improved photolithography. FIGS. 2a-2d shows the most common manufacturing process used to create a FET. A stock of films is deposited upon the wafer or substrate 110 as illustrated in FIG. 2a. First a thin dielectric 112, usually a thermal oxide (Tox) is grown on the substrate 110. Then the gate material 114 is deposited, which is usually a polysilicon. Then a photoresist 116 is spun on. FIG. 2b shows the lithography process. The photoresist 116 is exposed to light energy through a mask, and when washed with a developer, the desired pattern 122 remains. This pattern exposes the layer underneath to the gate electrode etch process as shown in FIG. 2c. Usually, this etch process is a RIE (Reactive Ion Etching). It removes exposed layer, yet keeps the features under the photoresist mask. Finally, the photoresist is removed and only the desired gate electrode remains. The width of the photoresist 122 was transferred directly to the gate 114, minus the etch-bias 118 from the RIE. The etch-bias is the difference between the initial photoresist (PR) CD 122 and the final gate CD 142. See FIG. 2d. 
Different etching processes and compositions can produce more or less etch-bias. A larger etch-bias produces smaller gate CDs. However, there is typically a cost associated with this desired result. Some compositions will produce large N-I (nested to isolated linewidth) offset deltas when the etch-bias is too high. Other compositions will produce undesireable sidewall profiles. A major problem of the RIE aggressively going after a large etch-bias is the complete removal of the photoresist mask during the etch. This results in “opens” or removal of the polysilicon gate feature completely in a localized or general area.
Another method for defining gate electrodes is with a hard mask process. FIGS. 3a-3d show that this method simply inserts a thin material 230 usually a dielectric, between the photoresist and gate, and this requires an extra etch step. Hard-mask gate definition is often used to enhance polysilicon gate profile and decrease aspect ratio so that removing bottom corner of gate material is easier. However, the same problems described above for soft-mask (PR) exist for hard-mask when etch-bias is aggressively pursued in order to achieve sub-lithographic features.
One particular current technique for achieving sub-lithographic gate CD involves a separate photoresist trimming step. Here the “as printed” resist is consumed by an oxygen plasma prior to RIE etching. However, there is a limit to how much the resist can be trimmed and the resist retain acceptable profiles. Projected demands for smaller linewidths cannot be met by current photo and RIE trim capabilities.
As the demand for smaller CDs continues, there is a need for new methodologies to produce smaller CDs. Achieving smaller photoresist CDs has proved very difficult as the current technology is at the end of the UV spectrum. Other methods for producing sub-lithographic features are desired. Bearing in mind these demands and deficiencies of the prior art, it would therefore be desirable to provide an improved method of forming a semiconductor device.